ISBN 9783843926492

978-3-8439-2649-2, Reihe Elektrotechnik

Jonas Diemer
Predictable Architecture and Performance Analysis for General-Purpose Networks-on-Chip

174 Seiten, Dissertation Technische Universität Braunschweig (2016), Softcover, A5

Zusammenfassung / Abstract

Many-core processor architectures are a promising option to overcome power and efficiency issues with previous single-core processor architectures. Networks-on-Chip are key to delivering efficient many-core architectures, as they address the major challenge of communication between the individual cores and other on-chip resources. Many-core architectures also address the computing performance needs of current emerging applications (such as advanced driver assistance or autonomous driving), but must offer increased timing predictability to facilitate real-time applications. For safety-critical applications, the real-time capability must be proven analytically.

Thus, this thesis aims at designing a predictable Network-on-Chip that allows the integration of general-purpose and embedded real-time applications and provide the necessary analysis to prove its real-time capability. For this, a design for a predictable Network-on-Chip is presented that is capable of providing latency and throughput guarantees to critical applications while improving the throughput of general-purpose applications. A simulative evaluation shows that this design significantly improves general-purpose throughput while retaining latency and throughput guarantees for embedded applications. A prototypical FPGA-based implementation of the Network-on-Chip design and integration into a many-core processor architecture demonstrates its feasibility and efficiency compared to simpler predictable Network-on-Chip designs.

To formally prove the real-time capability, the Compositional Performance Analysis theory is generalized to cover Networks-on-Chips and comprehensively formulated. pyCPA, a modular analysis framework is presented that allows the application of the analysis to real-world example systems. Furthermore, compositional performance analysis formulations are derived for typical Network-on-Chip switches with multi-stage arbitration mechanisms and also the proposed Network-on-Chip architecture. With this, throughput and latency guarantees for the proposed Network-on-Chip are proven, including a computation of the required network configuration. Finally, an outlook is provided of how the contributions of this thesis can be further exploited in future many-core architectures but also off-chip networks such as Ethernet.