ISBN 978-3-8439-2990-5

978-3-8439-2990-5, Reihe Elektrotechnik

Sandro Pinarello
Adaptive strategies for enhancing the efficiency of radio frequency power amplifiers in back-off operation

191 Seiten, Dissertation Universität Erlangen-Nürnberg (2016), Softcover, B5

Zusammenfassung / Abstract

In a market characterised by increasing volumes of shipment of modems and front-end devices for mobile applications, having strong differentiators from the competitors can leverage the market shares eventually won. Two differentiators are motivations to the research presented: current consumption and cost. Reduction of current consumption during communication can be addressed by increasing the efficiency of the PA especially at an output power lower than the maximum one (back-off). Reduction of the costs can be pursued by looking at opportunities for SOC integration (CMOS).

Starting from the limits of the classical load-line theory an extended model for analysis of PA efficiency is presented, which accounts for any knee-voltage and for the operation at back-off. Three methodologies are then identified dynamic voltage biasing (DVB), dynamic current biasing (DCB), dynamic load matching (DLM), which are suitable for being combined to enhance PA’s efficiency. Load-pull large-signal on-wafer tests on a SiGe device shows the combination of DVB and DCB is the best performing strategy with an appreciable 70% PAE for 16dB power back-off range. On CMOS the efficacy of this combination is reduced with a 60% PAE for only 6dB back-off. The non-linear parasitics of the CMOS technology are identified to be the limiting factor which can be compensated by properly combining DVB, DCB, and DLM: this extends the 60% PAE to 18dB of back-off range.

The experimental investigations show the factors limiting the PAE when reducing biasing conditions are non-linear parasitics and the poor current’s density. Accordingly a reconfigurable stage in CMOS technology with improved efficiency at back-off is presented, which features design changes to reduce the influence of the factors affecting PAE negatively. On-wafer tests on proof-of-concept structures highlight the possibility of saving between 25%-60% battery current in the 7-26dB back-off range.

A new concept for harmonic phase reference is also presented, which allows a cheap yet profitable way of achieving time domain measurements in a load-pull test-bench.