ISBN 978-3-8439-3119-9

978-3-8439-3119-9, Reihe Elektrotechnik

Michael Zwerger
Verification and Synthesis of Analog Power-Down Circuits

162 Seiten, Dissertation Technische Universität München (2017), Hardcover, A5

Zusammenfassung / Abstract

This thesis investigates electronic design automation algorithms for the verification and synthesis of analog power-down circuits. The methods build upon a new structural graph model that models the static circuit behavior. The verification method detects floating nodes, leakage currents and reliability problems due to electrical stress. The synthesis method allows automatic computation of a complementary power-down circuit for a given circuit.