ISBN 978-3-8439-4473-1

978-3-8439-4473-1, Reihe Elektrotechnik

Radu Ciocoveanu
Highly Integrated Millimeter-Wave CMOS Transceiver Frontend-Circuits for Radar and Communication Systems

185 Seiten, Dissertation Universität Erlangen-Nürnberg (2020), Softcover, B5

Zusammenfassung / Abstract

The large unlicensed 7 GHz bandwidth (BW) from the 57 GHz to 64 GHz band represents a very attractive option for Short Range Radar (SRR), which can be used in battery powered portable devices. The target application using SRR is gesture recognition, which can unlock a new level of human-machine interaction. Furthermore, the upcoming 5th generation mobile communications system (5G) system promises very large data rates and bandwidths by tapping for the first time into Millimeter-Wave bands.

Therefore, the focus in this thesis is to tackle the challenges presented by CMOS implementations of Millimeter-Wave front-ends. On the receiver side, the low linearity of active mixers in CMOS is addressed and a dynamic biasing circuit to minimize the performance variation with process, voltage and temperature (PVT) is proposed. Moreover, the active mixers implementations in CMOS have a high 1/f noise and to reduce it, an innovative waveform shaper is designed. On the transmitter side, transistor stacking is pursued to address the lower output power due to limited supply voltage. Furthermore, a differential stacked power amplifier (PA) topology with harmonic control is used to achieve high output power and efficiency from a CMOS silicon on insulator (SOI) technology. Finally, a 60 GHz transceiver for radio detection and ranging (radar) applications with integrated RF front-end and analog baseband (ABB) is proposed. Moreover, a 28 GHz front-end module (FEM) for 5G applications is implemented and measured.

This work presents the design and implementation of integrated transceivers and building blocks for 60 GHz short-range radar applications in 28 nm bulk CMOS, 45 nm partially depleted (PD) SOI and 22 nm fully depleted (FD) SOI. Also, the design and implementation of building blocks for 28 GHz, 5G applications in 45 nm PD SOI is presented.